Lectures: MWF 9:30 - 10:20, 215 College
What goes on behind the scenes after you compile your
program? Students learn how a computer is put together, and
the relationship between the hardware and the instruction
sets. We study the MIPS machine language and the high level
organization of a fully pipelined modern RISC machine:
including: ALU design, CPU design, pipelining, memory
organization, cache and virtual memory, I/O, and methods of
measuring the effectiveness of these features.
Exams: There will be one midterm (25%)
and one final examination (35%). The final will be on
Wednesday, May 6, 9:00 AM.
Assignments: Homework assignments and
programs are worth 40% of your grade. You should do
these with a partner, and one grade will be given to both people
in each group. All programs should be written using SPIM or
MARS, both simulators for the MIPS architecture. You can
for whatever computer you own. PCSpim, an old version of
SPIM for PCs, should already be loaded on the machines in the lab
and it is what I use, but there is a new multi-platform version
called QtSpim. If you download PCSpim, make sure that the
settings are set as shown below so that the programs I run in
class will all work. Delayed branches is kind of
"half-checked". To get authentic assembly translation, it
needs to be checked. But to run a program it is easier to leave it
unchecked, or else you will need blank "nop" instructions after
every branch. Best to leave it unchecked if in doubt, or ask me.
In QtSpim, you need to uncheck MappedI/O. If you get an
error message in QtSpim saying that __start label is defined
twice, try replacing __start: with main:
You should demo your programs for me personally. For written
problem sets, you should hand them into me personally (before midnight
of the day they are due). Late
assignments will not be accepted or graded.
Finally, read our department's academic
guidelines before you submit any written work or demonstrate
Grading: Your grade is 25% midterm, 40% homework, and 35% exam. You can guarantee an A- or better with 90%, a B- or better with 80% etc. I may curve these numbers in your favor, if I feel it is warranted.
Special Dates: There will be no lecture
Wednesday, April 15 due to Passover.
Reference LinksMIPS Simulators: Download SPIM Download MARS Online manual for MIPS using QtSpim.
MIPS Reference: Quick Reference MIPS Opcode LookUpSample Programs + Other Helpful Links
"Cheat Sheet"MIPS Reference (Green Card from the text)
Hardware: My Hardware Notes MultiCycleDataPath FiniteStateMachineMultiCycle Practice Adding Instructions to MultiCycle Implementation
SingleCycleDataPath PipeliningDataPath PipeliningHazards DataHazard-Forwarding
Cache Review Slides Practice with Cache and Virtual Memory
Reading Assignments: These assignments explain why programmers should know architecture. Read them the first week of class, and read them again after the tenth week. I mean that! You will learn a lot each time. If you get anything out of this class, it should be the notion that architecture is important for programmers!
Written Assignments and Programming: Assignment 1 Assignment 2 Assignment 3 Assignment 4 Assignment 5 Assignment 6 Assignment 7
CISC versus RISC. Measuring Performance.
Why do Programmers Need to Know About Computer Architecture?
Intro to SPIM Simulator Basics: Instructions, Data, and Directives.
Basic MIPS Assembly Language: Arithmetic and Memory Operations, Control Structures, Arrays.
Chapters 2 and 3,
Online QtSpim/MIPS manual
||Data Representation - Two's
complement, Sign Magnitude, Floating Point, ASCII.
More MIPS: Registers and Address Modes. Data Structures, Stacks, Procedures, Stack Frames, Run-time Stack, Parameter Passing.
Appendix A: 5-11
Machine Language and MIPS Instruction Formats. Assemblers - One and Two Pass.
Friday, March 20
Data Path and Control Architecture - Single versus Multi-cycle.
MultiCycleDataPath FiniteStateMachineMultiCycle SingleCycleDataPath
Chapter 4: 1-4, Appendix D: 1-5,
My Links (see left)
Pipelining - An Efficient CPU, Performance Measures, Structural Hazards, Data Hazards, Forwarding, Branch Hazards, Hazard Handling: Forwarding, Branch Predictions, Compiler Rewrites, Stalls and Nops.
|Chapter 4: 5-8
Memory Architecture - Hierarchical Structures: Cache and Virtual Memory.
|Chapter 5: 1-8
(If time allows) Cloud Computing and Parallel Processing