Working on real hardware is an
experience for which there is no substitute. Nowadays, most
hardware design uses software and various languages like VHDL.
Nonetheless, despite the bugs and challenges that come with real
electronics, it is more fun to work with hardware. And, in a
liberal arts CS major, it is this class or never for
Your project kit comes with a power
supply, wires, integrated circuit (IC) chips, resistors,
capacitors, LEDs, and a "breadboard" in which to insert these
components. A breadboard is a device with holes and channels
allowing easy connection of wires to chips. I will show how
it all works in class. Your group is responsible for the
equipment that you use, and you must return it at the end of the
semester exactly as you received it. Damaged or lost kits
will set you back $175; be responsible.
Your project kit leads you through the design of a very simple computer. The computer is very simple in function. It has a simple ALU that just increments; it uses RAM only for instructions, not for data; it has two registers A and B to store data; and it has a mere four instructions: INCA, INCB, MOVAB, and MOVBA. (Some of your kits include other instructions - but you do not need to implement these). Indeed, the computer kit does not have the power to do if-statements, loops, input/output, or use RAM for data. Nonetheless, despite the simplicity of this machine, you will find debugging each stage a challenge, and you should plan to leave plenty of time for slow and steady progress. Besides your own careless wiring errors or misunderstandings, there are also more difficult problems to debug such as breadboard defects, broken wires, power instability, or a malfunctioning chip. Most bugs are fixed with patience, care, rereading, and/or rewiring. For example, each chip can be tested separately to make sure it functions before incorporating it into the breadboard. For a particularly severe bug, I may send you over to the Physics department to use an oscilloscope to pinpoint subtle errors. If a bug is caused by an unfixable defect in the kit, I will not hold you responsible; I will always try to provide spare replacement parts when needed.
The kit comes with a manual, but the
hints and details below based on classroom experience, offer you
very useful supplementary information, not all of which can be
found in the manual. You may also find the designer's site Yunten Labs to be
a useful reference. Finally, it is worthwhile for each group
to invest in a good pair of wire strippers and a magnifying glass
with a light.
Grading and Getting Your Work Checked
The project has five stages, each one clearly indicated in your manual. There is a sixth stage that we do not implement. It is a good idea to show me your progress after each "stage" of the project so that in case anything breaks late in the game, you still get credit for earlier work. If you wait until the end to show me everything and it doesn't work, I won't be able to tell how much you finished successfully. Taking a movie on your cell phone is a quick way to record correct functionality. Note: if your hardware at any stage has bugs that do not allow you to get it working after your best efforts, you can still get partial credit for that stage (and future stages) by wiring it up and explaining to me in person what it is supposed to do.
In this picture,
a complete project through stage 6 is shown, but remember you need
only complete stages 1 through 5. Stage 6 includes the small
breadboard on the right with five chips and it handles input and
output and interrupt processing usually handled by the operating
Each of the five stages you must
implement is comprised of a row of chips. Leave space on the
right side of the rows in stages 1 through 4 because stage 5 needs
to use some space on the right side of two of these rows.
The function of each row of chips is summarized below:
Five Stages and Testing
Stage 1. (4 chips) These
chips simulate a clock that generates a ripple timing signal
0-9. The original pulse is created using a purposeful glitch
from three consecutive not gates. The first six signals T_0
through T_5 are monitored by LEDs.
To test this stage, you should see a
ripple counter lighting six LED's on and off in order with a blank
count of four (a total of ten ticks) before it cycles and starts
again. There is sometimes a glitch if you try to monitor all
the chips' output in this stage. In particular it is often
difficult (impossible?) to monitor the 7490 counter chip
accurately with LEDs. Instead, just monitor the first chip
(one blinking light) and the last chip. Also, the T_0 coming
out of the last chip will (eventually) need five splices, so make
sure to move its output to a fresh column.
Follow the manual carefully.
Depending on the chips you have, some require resistors to pull
current effectively and some do not. In particular, the
outputs of the 75LS05 chips require resistors to pull-up the
current. Otherwise, you will not see the blinking lights on
your LEDs from the rightmost 75LS05 chip on stage 1.
Occasionally, some students find
erratic behavior in the circuit unless they touch the top of the
capacitor with their finger! I do not know why this glitch
occurs, but be aware of that possibility. Some students
report being able to fix this glitch by adding a resister between
the top of the capacitor and power. Others report success with a
wire connecting ground to the top of the capacitor. Either
method is better than just using your finger.
Video of Stage 1 working
Stage 2. (5 chips)
These chips include a register holding the program counter (PC),
an adder (ALU), and a side register to hold the result of the
adder. Each register connects to the bus via a buffer register, so
that each register uses two chips. The purpose of this part of the
data path is to increment the PC. The PC sends input to the
ALU; the other input of the ALU is set to 0000 (4 grounds);
and the carry_in is left to default high (1) and needs no
connection. Thus, the ALU effectively adds 1 to the
PC. This addition is done in two steps using the states T_0
and T_1. At T_0, the PC value moves onto the bus and into
the adder, at T_1, the incremented value moves back to the PC. The
"side" register is not used in this stage, but will be used later
when you stat decoding specific instructions.
To test this stage, monitor the data
lines of the PC. You can do this by monitoring the bus using
LEDs with resistors. You should see the PC increment in
binary after every complete 6 cycles. The change occurs in
the first two cycles (T_0 and T_1).
Video of Stage 2 working
Note that in later stages of the
project, the SUM_in and SUM_out signals on the Sum register and
the output buffer to its right, which now come from T_0 and T_1,
will eventually come from Or gates and not directly from the
clock's T_0 and T_1. Later on, in cycles T_2 through
T_5, more interesting things will occur, depending on the
instruction being executed. Right now, we are only
controlling the incrementing of the PC which will happen with
every instruction independent of what the instruction does.
As is the case in Stage 1, sometimes
Stage 2 will not work correctly if you simultaneously monitor the
signals from Stage 1. So, if you are at your wit's end,
always try to remove all LEDs except the ones monitoring the
section you are testing.
Stage 3. (6 chips)
These chips are three registers with associated buffers connected
to the bus. They are the MAR, and two side registers A and B
that are used to hold data results of instructions. This computer
does not use RAM for data (only for program instructions).
The data path of this stage is used to read instructions from
memory. This fetching occurs during T_0 and T_1,
simultaneously withe PC increment..
To test this stage, monitor the data lines of the MAR, and you should see it mimicking the binary values on the PC. The MAR values should be behind the PC values by one complete set of 6 cycles. Note that in this stage the "out" control signals on MAR, A, and B should be grounded to prevent these buffers from spilling values onto the bus. Only one buffer should ever output to the bus at a time, and this will be controlled in stage 5 by the control unit. Now, however, you need to manually ground these lines to keep them off the bus. The MAR_out signal stays grounded throughout the project, but A_out and B_out will eventually be fed from logic gates in the control unit of stage 5. Finally, MAR_in should be connected to T_0. Note that MAR_in is not shown explicitly on the 7475 chip diagram, MAR_in (marked red) should be connected to pins 4 and 13 (also marked red) to activate all 4 (flip-flops) bits. You can connect 4 and 13 together to manage this. Finally, A_in and B_in should be left open for now. They too will eventually get signals fed from the control unit. In general, it does not hurt to leave the "in" control lines open (disconnected is default open) because they can all read from the bus simultaneously without any errors. However, it would be a disaster to have more than one chip write to the bus at the same time. That is why we make sure to have at most one of the "out" control lines on, and ground the rest when testing this stage.
Video of Stage
Stage 4. (4 chips) This
stage includes a 16 4-bit memory (RAM) chip, two dip-switches to
control the input to the RAM, and three chips (two inverters and
one decoder) to generate control signals from the instructions
coming from RAM. Recall, that this computer does not store "data" in the
RAM; it stores only program instructions in RAM. The
MAR sends an address to the RAM and the RAM sends out the contents
of that address in binary. The contents represent an
instruction. These binary instructions are decoded into
unary and a particular instruction will fire one of the Isig
lines, Isig_0, Isig_1, Isig_2, Isig_3. Note that Isig_5 and
Isig_4 do not get used. Also, be careful to set the dip switches
to off on AD_0 through
AD_3 when running your program. They are set to on only when storing the
Note this stage can and should be
tested independently of the other stages. That is, you must power just this row
when testing this stage. Indeed, it can be tested correctly
even if you have a bug in one of the earlier stages. You
should be able to store program instructions (4 bits) into any of
the 16 RAM locations, and observe that these instructions are
indeed stored correctly.
Video of Stage 4
Stage 5. (5 chips) The
fifth project is the control unit, and in contrast to the other
stages, does not appear in its own row. Instead it is
distributed on the right side of the first four rows. There
are five chips in this stage consisting of various ANDs and ORs
that allow you to generate control signals to registers A and B,
the MAR, the adder, and their buffers. You may not need to
use all these chips, depending on how many instructions you try to
implement. Your computer should implement the four
instructions: INCA, INCB, MOVAB, and MOVBA. It is this
stage that will finally connect to all the open control lines left
from earlier stages. (that is, A_in, B_in, A_out, B_out,
Sum_in, Sum_out, etc.) Remember to remove any grounded
inputs that had been connected temporarily to these control
lines. Notice that the INCA and INCB instructions get
implemented in cycles T_2 and T_3, and the MOVAB and MOVBA
instructions in just T_2.
You decide which Isig line fires which
instruction. You will use Isig_0, Isig_1, Isig_2, and Isig_3
for the four different instructions. For example, if you
assign Isig_0 to MOVAB, then connect its signal to the MOVAB arrow
on pin 1 of the 7408 AND gate.
Testing this stage requires you to
power up the whole computer. You should first test each
instruction separately. Make sure that you disconnect the
dip-switches from memory when you run your computer. There
can only be one input to the RAM address pins at a time. When you
program the computer (stage 4) the connections are from the
dip-switches, but when you run the computer, the connections are
from the MAR. You can disconnect the dip-switches by simply
removing the switches from the breadboard. The manual
suggests disconnecting the dip switches by setting them all to 1,
which effectively disconnects them too, but that is not the
The Complete Project
INCA INCA MOVAB
INCB INCB INCB MOVBA
Cycle 0: PC goes to bus and gets incremented. MAR gets old value of PC from bus.
Cycle 1: PC gets new value. Instruction at location PC is fetched from memory.
Cycles 2-3: The instruction is decoded by the control unit and executed.