CSC 221 - Computer Logic and Organization

Shai Simonson    306 Stanger    (508) 565-1008

Email:  shai@stonehill.edu

Homepage: http://www.stonehill.edu/compsci/shai.htm


Lectures:  MWF 10:30 - 11:20,  209 Stanger

Text:  Digital Logic and Microprocessor Design with VHDL, 1st edition, by Enoch Hwang, Thomson.
           Author's Web Site - Review, Extra practice problems and Solutions.

Grading:  There are 500 total points you can earn in the course half from exams and half from project and homework aasignments. I will discuss in class how I calculate final grades, includign any details about "curves".

Exams:  There will be one midterm (20% - 100 points) and one final examination (30% - 150 points).  The final will be Friday, December 15 at 9 AM.

Goals:  To understand the theory and application of digital electronics in order to build computers.  You will study the design of two small computers on paper, and build a small prototype of a computer yourself on a "breadboard".

Teaching Assistant: 
The teaching assistant(s) are Sam Bradford, Stephen MacSwain, and Greg Costello.   The TA(s) will check homework assignments, assist with "breadboard" lab-days in class.  Feel free to email any TA to set up 1-1 meetings for help with HW or breadboard issues.  In addition, Greg will be available Wednesday evenings in 308 at 7:00-9:00.  Sam and Steve hours are Mondays 7:00-9:00.

Assignments and Project:   Your project and all homework assignments will be done in groups of three, with one grade given to the group.  Read our department's academic integrity guidelines before you hand in any written work. The project is 15% (75 points) of your total grade and the written homework is 35% (175 points).  There are 5 written homework assignments -- each is 7% (35 points).

Special Dates:   Fridays September 22, and October 6 and 13, are Jewish holidays. I will use these as lab-days. The TA(s) will be around to answer questions and do some review and explanation of the hardware kits.

Reference Links

Cool Circuit Simulator

Here is the Index

Electronic Components and Circuit Diagram - Self Study Free Downloadable Tool for Circuit Design and Simulation
Reference Chart for Chip Specs
Minecraft Circuits
Free Simulated Breadboard
History of Transistors and Silicon Valley -

Assignments


Asg1
Asg2
Asg3
Asg4
Asg5


Take-Home Final Question (20% of Final Exam)

Bring in your solution to the final.  You may use your notes and book.  You must work alone.

Design an alternative (Mealey Machine style) control unit for the EC-2 computer described in section 12.3 in your text pages 485-488 (or 380-382 - edition 2).  Your control unit should have only 4 states, 0-3,  corresponding to the four levels of the finite state machine on page 485 (edition 2- 380).  You should use two flip flops to represent the state.  You should hand in a finite state machine diagram, next state table, excitation equations, output table, output equations, and final circuit.  Use the techniques of chapter 7 to implement the finite state machine using Karnaugh maps to minimize equations and circuits.

Hints and comments: 
  1. Note that in class we designed two control units for my 8 op-code computer: a Moore Machine and a Mealey Machine.  This alternative finite state machine for EC-2, which I am asking you to design here, is similar to the Mealey Machine alternative we designed in class for my computer.
  2. Because of the smaller number of states, the output equations will depend not only on the current state but also on the opcode, i.e., a Mealy Machine.  The output chart on page 487(e) (edition 2 - 381 (e)) will only have four rows for the four states labeled 00, 01, 10, and 11. 
  3. Also, the output chart will have fewer constant 0's and 1's and more entries like (IR7 IR6' IR5 + IR7 IR6 IR5').  By the way, the entry (IR7 IR6' IR5 + IR7 IR6 IR5') is the actual value that you should have in the column labeled JMPMux and row labeled state 11.  It means that whenever the instruction is Jz (101) or Jpos (110), the input to the PC comes from the IR rather the incrementing unit, see page 483 (Edition 2 - 378).  
  4. Note that the PCload signal is controlled by the AC=0 and AC>0 signals, so JMPMux only controls the source of the input to the PC but not whether that input is actually loaded.  If a branch is not taken, PCload would be 0, the PC would continue to hold its normal incremented value, and the JMPMux value is irrelevant.

Brief Syllabus

Week

Topics

 Reading

1 Introduction - How to Build a Computer:   Theory, Number Representation, Gates, Circuits, VHDL.
Chapter 1
2
Electricity and Hardware:  Breadboards, Gates, Chips, Ohm's Law, Voltage, Current, Resistance.
Yunten + Class Notes
3 Boolean Algebra, Sums of Prodcuts, Products of Sums, Karnaugh Maps, Timing Diagrams
Chapters 2-3
4-5
Common Combinational Circuits: Arithmetic and Logic Unit, Decoders, Tri-State Buffer, Multiplexers, Comparators, Shifters.
Chapter 4
6
Project Building Orientation: Basic Electronics, Breadboards, Voltmeters, Wires, LEDs, Resistors, Power Supplies.
Yunten Notes
7
ROMs and PLA's:  General Combinational Circuit Synthesis

Sections 5.6-5.7
(missing in second edition)
Chapter 6
(Chapter 5 in second edition)
8
Basic Sequential Circuits:  Clocks and Timing, Latches and Flip-flops:  SR, D, JK, T flip flops, Frequency Dividers.
Chapter 6
(Chapter 5.1 - 5.11 in second edition)
9
More Sequential Circuits:  Finite State Machines (Mealy and Moore machines) as Control Circuits. Chapter 7
(Chapter 6 in second edition)
10
Midterm Examination

11-12
Common Sequential Circuits:  Memory - Registers, Counters, RAM, ROM.
Chapter 8
(Chapter 5.12-5.16 second edition)
13-14
Simple General Purpose Microprocessors:   Machine Language, Data Path, Control Unit - FSM's Revisited.
How to Build a Computer - Putting it All Together.
Chapter 12
(Chapter 8 in second edition)
15
Project Building:   Manual Design of a Simple Computer: ALU, Registers, RAM, Bus, I/O, Interrupts.
Yunten Notes