CS 221 - Computer Logic and Organization

Shai Simonson    306 Stanger    (508) 565-1008

Email:  shai@stonehill.edu

Homepage: http://www.stonehill.edu/compsci/shai.htm


Assignment 4 - 35 points

Due: Before Thanksgiving Break


Chapter 6:  Pages 211-212

Problems: 1, 3, 9 (skip the VHDL), 11.            (points; 4, 3, 6, 3)

Hints:  For 9 you may find it easier to build the JK out of D flip-flops using a FSM idea, and then replace the D flip-flops with SR latches as we did in class.
For 11, see section 6.11 to incorporate gate time delays correctly. You may assume that at the start D' , Q , and Q' are 0, 1, and 0 respectively.  That is, assume, that the D has been high for long enough for the other signals to start at stable values.

(Edition 2:  Chapter 5:  1, 2, 6, 7 (see section 5.17 to incorporate gate delayes correctly), 8   (points: 3, 2, 2, 3, 6)  )

Chapter 7:  Pages 265-273

Problems: 2, 3, 8, 13.                                    (points: 6, 7, 3, 3)

(Edition 2:  Chapter 6:  2, 3, 4, 8                    (points: 5, 8, 3, 3) )