CSC 304 - Computer Architecture

Shai Simonson    306 Stanger    (508) 565-1008

Email:  shai@stonehill.edu

Homepage: http://www.stonehill.edu/compsci/shai.htm


Lectures:  MWF 10:30 - 11:20, 001 Stanger

Text:  Computer Organization and Design, 4th edition, by Patterson and Hennessy, Elsevier.  Instructor site.

Exams:  There will be one midterm (25%) and one final examination (35%). The final in Spring 2012 will be Friday May 11, 9:00 AM.

Assignments:  Homework assignments and programs are worth 40% of your grade.   You should do these with a partner, and one grade will be given to both people in each group.  All programs should be written using SPIM, a simulator for the MIPS architecture.  You can download your own copy of SPIM for whatever computer you own.  PCSpim, an old version for PCs, should already be loaded on the machines in the lab and it is what I use, but there is a new multi-platform version called QtSpim.  Whatever version you download and use, make sure that the settings are set as shown below so that the programs I run in class will all work.

You should email your assignments to cs303@stonehill.edu, and not to my personal email.  Late assignments will not be accepted or graded.  Please send each program in a separate text file attachment.  For problem sets, you should hand them into me personally (before midnight of the day they are due).  Do not leave anything under my door or you may not get credit for handing it in on time.  Finally, read our department's academic integrity guidelines before you hand in any programs.

Warning about the book's exercises:
  The book's problems may seem vague and/or difficult at first glance.  Ask me if you have any doubts about how to do a problem.  I will review any solution one on one or in class, as you prefer.

Course Description:  What goes on behind the scenes after you compile your program?  Students learn how a computer is put together, and the relationship between the hardware and the instruction sets.  We study the MIPS machine language and the high level organization of a fully pipelined modern RISC machine:  including: ALU design, CPU design, pipelining, memory organization, cache and virtual memory, I/O, and methods of measuring the effectiveness of these features.

Goals:  To understand the gap between programming and computer hardware design. To appreciate how understanding computer architecture will make you a better programmer.

Special Dates:  Class on Friday, April 13 is cancelled due to Passover.  I will be in France on Friday March 2. I may schedule the midterm on that date.

 

Reference Links

Download SPIM        SPIM Quick Reference   MIPS Opcode LookUp    MIPS Floating Point and IEEE 754   Online Binary Calculator


Sample Programs

multiply   helloworld   avg     io    strings    traverse_array   branches     loop       palindrome       long_mult       sort         address modes

Assignments

Read Paul Hsieh's Code Optimization Page
Concentrate on the last page. It explains why programmers should know architecture.

Assignment 1   Assignment 2   Assignment 3    Assignment 4    Assignment 5   Assignment 6   Assignment 7
 

Brief Syllabus

Week

Topics

 Reading

1
CISC versus RISC.  Measuring Performance. 
Why do Programmers Need to Know About Computer Architecture?


Chapter 1,
Online


2-3

Intro to SPIM Simulator Basics:  Instructions, Data, and Directives. 
Basic MIPS Assembly Language:  Arithmetic and Memory Operations, Control Structures, Arrays.


Chapters 2 and 3
4 Data Representation -  Two's complement, Sign Magnitude,  Floating Point, ASCII.

Chapter 2

5-6
More MIPS:  Registers and Address Modes.  Data Structures, Stacks, Procedures, Stack Frames, Run-time Stack, Parameter Passing.

Chapter 2, Appendix B
7

Machine Language and MIPS Instruction Formats.   Assemblers - One and Two Pass.

Chapter 2,  Appendix B

8

Midterm Examination.                  
Exceptions

Date: Friday, March 2
Appendix B

9-10

Data Path and Control Architecture - Single versus Multi-cycle.  Hardwired vs. Microprogramming.


Chapter 4,
Appendix D (on disk)
11-12
Pipelining -  An Efficient CPU, Performance Measures, Hazard Handling.  Implementation.

Chapter 4
13-14
Memory Architecture - Hierarchical Structures:  Cache and Virtual Memory.

Chapter 5
15
I/O Architecture - Design and Performance.  Review

Chapter 6