Professor Shai Simonson - CSC 304 - Computer Architecture



Assignment 7

Memory Hierarchies:  Cache and Virtual Memory

 

Due: By the last day of class

In the book.  (15 points)


Chapter 5:  5.2 (only parts 1-3), 5.3, 5.5, 5.7, 5.11 (only parts 1-4), 5.13.



1.    
Refer to the Page table, TLB, and Cache table below to answer these questions:


What would happen if a CPU tries to access the following addresses? 

 

a)      0x0364 

 

b)     0x033D

 

c)     0x036B


For each case:  Is there a TLB hit or miss? Is there a cache hit or miss?  What is the result of the memory access or is there a page fault?

 



Addressing

  14-bit virtual address

  12-bit physical address

Page size = 64 bytes




 

Page Table (first 16 entries only)

VPN

PPN

Valid

VPN

PPN

Valid

00

28

1

08

13

1

01

-

0

09

17

1

02

33

1

0A

09

1

03

02

1

0B

-

0

04

-

0

0C

-

0

05

16

1

0D

2D

1

06

-

0

0E

11

1

07

-

0

0F

0D

1

 

TLB

16 entries

4-way associative

 

 

Set

Tag

PPN

Valid

Tag

PPN

Valid

Tag

PPN

Valid

Tag

PPN

Valid

0

03

-

0

09

0D

1

00

-

0

07

02

1

1

03

2D

1

02

-

0

04

-

0

0A

-

0

2

02

-

0

08

-

0

06

-

0

03

-

0

3

07

-

0

03

0D

1

0A

34

1

02

-

0

 

Cache

16 lines

4-byte line size

Direct mapped




Idx

Tag

Valid

B0

B1

B2

B3

Idx

Tag

Valid

B0

B1

B2

B3

0

19

1

99

11

23

11

8

24

1

3A

00

51

89

1

15

0

-

-

-

-

9

2D

0

-

-

-

-

2

1B

1

00

02

04

08

A

2D

1

93

15

DA

3B

3

36

0

-

-

-

-

B

0B

0

-

-

-

-

4

32

1

43

6D

8F

09

C

12

0

-

-

-

-

5

0D

1

36

72

F0

1D

D

16

1

04

96

34

15

6

31

0

-

-

-

-

E

13

1

83

77

1B

D3

7

16

1

11

C2

DF

03

F

14

0

-

-

-

-

 

 


back

 


shai@stonehill.edu

http://www.stonehill.edu/compsci/shai.htm